As circuit complexities increase, a mixed type of circuit has evolved which integrates a digital core with analog circuitry. The digital core may comprise programmable logic circuitry, a microprocessor, or a finite state machine among other things. The analog circuitry includes comparators and digital-to-analog or analog-to-digital converters. For example, programmable power sequencers have been developed that contain a programmable logic core comprising a programmable AND array. The programmable AND array is integrated with comparators whose outputs are required by the AND array to properly control the power sequencing of devices.
As is common with digital systems, the programmable logic core includes synchronous devices such as flip-flops that must be powered-up in a particular binary state denoted as reset. Accordingly, digital systems typically include a power-on reset (POR) circuit that senses the onset of power during a power-up of the system from an off state or from an on state in which the power has fluctuated below an operating threshold. The POR circuit responds by asserting a reset signal for a predetermined or variable period of time, which may be denoted as the POR period. Typically, a POR circuit includes a Schmitt trigger or some other hysteresis device to control the assertion of the reset signal. Given the presence of a POR circuit, the digital devices that must be in reset upon being powered-up are protected from “waking up” into rogue, unpredictable states. Without a POR circuit, these rogue binary states cause malfunctions, glitches, and other undesirable effects. During the POR period, input/output terminals to the device are typically tri-stated (driven into a high impedance state).
Assuring the performance of synchronous digital circuitry is not the only concern during power-up in a mixed digital/analog device such as a programmable power sequencer. The analog circuitry may also require a stabilization period after power-on before proper operation is reached. For example, a voltage reference such as from a bandgap reference requires a stabilization period alter power-on (or equivalently, an equilibrium period). As is known in the art, a bandgap reference provides a reference voltage that depends upon two voltages having opposing temperature dependencies. One voltage increases with increasing temperature whereas the other voltage decreases with increases increasing temperature. By properly compensating these voltages, the bandgap reference provides a reference voltage that is stable with respect to temperature. Bandgap references include a differential amplifier that responds to the difference between the voltages with the opposing temperature dependencies. In turn, the output of the differential amplifier controls the compensation of these same voltages within a negative feedback loop. This feedback loop takes time to settle and reach equilibrium. The amount of time necessary for equilibrium may be denoted as the bandgap period. Additional time may be required for other reasons such as settling time on output filters or buffers to allow them to reach their requisite accuracy.
Although the bandgap period and the POR period begin at the onset of power-up and run concurrently, they may be dramatically different in length. The length of the POR period will generally depend upon how much time it takes for VCC to become stable as supplied by the corresponding power supply. The VCC voltage may rise fairly rapidly, often around 0.5 volts per micro-second (μsec).
Accordingly, the POR period will comprise a certain number of micro-seconds, for example 100 μsecs. On the other hand, because the bandgap period depends upon the time required to stabilize a reference voltage, the bandgap period will typically be substantially longer, ranging from a few to as many as ten milliseconds (msecs). To assure proper functioning of both the digital and analog circuitry, the POR period for a mixed digital/analog circuit such as a programmable power sequencer is typically extended to be sure the bandgap period is satisfied before releasing the reset signal. Recall that the input/output terminals (also denoted simply as “inputs” or “outputs”) of the device are tri-stated during the reset period. This leads to a problem in that the input/output terminals may be pulled either high or low by external devices during this extended reset period. Upon release of the reset signal, an input or output may thus be in an unexpected rogue binary state, thereby causing glitches and malfunctions. Moreover, this problem will also be encountered should the analog circuitry comprise something other than a reference voltage source so long as the period needed to stabilize the analog circuitry is long enough to allow tri-stated inputs or outputs to be pulled by external devices into unexpected binary states. For example, waiting for calibration of analog circuitry or offset cancellation procedures may also create a disparity between the POR period and the readiness of the analog circuitry.
Accordingly, there is a need in the art for improved power-up techniques for mixed digital/analog circuits.